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High-Performance Architecture for Concurrent Error Detectio..:
SUGAWARA, Takeshi
;
HOMMA, Naofumi
;
AOKI, Takafumi
.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A (2011) 10 - p. 1971-1980 , 2011
Link:
https://doi.org/10.1587/transfun.e94.a.1971
RT Journal T1 <Title>High-Performance Architecture for Concurrent Error Detection for AES Processors</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transfun.e94.a.1971&Exemplar=1&LAN=DE A1 SUGAWARA, Takeshi A1 HOMMA, Naofumi A1 AOKI, Takafumi A1 SATOH, Akashi PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2011 SN 0916-8508 SN 1745-1337 JF IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences VO E94-A IS 10 SP 1971 OP 1980 LK http://dx.doi.org/https://doi.org/10.1587/transfun.e94.a.1971 DO https://doi.org/10.1587/transfun.e94.a.1971 SF ELIB - SuUB Bremen
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