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1 Ergebnisse
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A Verification-Aware Design Methodology for Thread Pipelini..:
JIAN, Guo-An
;
CHIEN, Cheng-An
;
CHEN, Peng-Sheng
.
IEICE Transactions on Information and Systems. E95.D (2012) 10 - p. 2505-2513 , 2012
Link:
https://doi.org/10.1587/transinf.e95.d.2505
RT Journal T1 <Title>A Verification-Aware Design Methodology for Thread Pipelining Parallelization</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transinf.e95.d.2505&Exemplar=1&LAN=DE A1 JIAN, Guo-An A1 CHIEN, Cheng-An A1 CHEN, Peng-Sheng A1 GUO, Jiun-In PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2012 SN 0916-8532 SN 1745-1361 JF IEICE Transactions on Information and Systems VO E95.D IS 10 SP 2505 OP 2513 LK http://dx.doi.org/https://doi.org/10.1587/transinf.e95.d.2505 DO https://doi.org/10.1587/transinf.e95.d.2505 SF ELIB - SuUB Bremen
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