I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
A Low-Power Packet Memory Architecture with a Latency-Aware..:
LEE, Hyuk-Jun
;
KIM, Seung-Chul
;
CHUNG, Eui-Young
IEICE Transactions on Information and Systems. E96.D (2013) 4 - p. 963-966 , 2013
Link:
https://doi.org/10.1587/transinf.e96.d.963
RT Journal T1
A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method
UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transinf.e96.d.963&Exemplar=1&LAN=DE A1 LEE, Hyuk-Jun A1 KIM, Seung-Chul A1 CHUNG, Eui-Young PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2013 SN 0916-8532 SN 1745-1361 JF IEICE Transactions on Information and Systems VO E96.D IS 4 SP 963 OP 966 LK http://dx.doi.org/https://doi.org/10.1587/transinf.e96.d.963 DO https://doi.org/10.1587/transinf.e96.d.963 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)