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A Novel VLSI Architecture for SPHIT Encoder:
Motupalle, Haritha
;
Badashah, Syed Jahangir
INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY. 10 (2013) 4 - p. 1522-1530 , 2013
Link:
https://doi.org/10.24297/ijct.v10i4.3252
RT Journal T1 <Title>A Novel VLSI Architecture for SPHIT Encoder</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.24297_ijct.v10i4.3252&Exemplar=1&LAN=DE A1 Motupalle, Haritha A1 Badashah, Syed Jahangir PB CIRWOLRD YR 2013 SN 2277-3061 JF INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY VO 10 IS 4 SP 1522 OP 1530 LK http://dx.doi.org/https://doi.org/10.24297/ijct.v10i4.3252 DO https://doi.org/10.24297/ijct.v10i4.3252 SF ELIB - SuUB Bremen
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