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1 Ergebnisse
1
Efficient ASIC Architecture for Low Latency Classic McEliec..:
Fallnich, Daniel
;
Lanius, Christian
;
Zhang, Shutao
.
IACR Transactions on Cryptographic Hardware and Embedded Systems. 2024 (2024) 2 - p. 403-425 , 2024
Link:
https://doi.org/10.46586/tches.v2024.i2.403-425
RT Journal T1 <Title>Efficient ASIC Architecture for Low Latency Classic McEliece Decoding</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.46586_tches.v2024.i2.403-425&Exemplar=1&LAN=DE A1 Fallnich, Daniel A1 Lanius, Christian A1 Zhang, Shutao A1 Gemmeke, Tobias PB Universitatsbibliothek der Ruhr-Universitat Bochum YR 2024 SN 2569-2925 JF IACR Transactions on Cryptographic Hardware and Embedded Systems VO 2024 IS 2 SP 403 OP 425 LK http://dx.doi.org/https://doi.org/10.46586/tches.v2024.i2.403-425 DO https://doi.org/10.46586/tches.v2024.i2.403-425 SF ELIB - SuUB Bremen
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