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1 Ergebnisse
1
An Efficient Configurable Hardware Accelerator Design for C..:
, In:
2022 IEEE International Symposium on Smart Electronic Systems (iSES)
,
Yanamala, Rama Muni Reddy
;
Pullakandam, Muralidhar
- p. 112-117 , 2022
Link:
https://doi.org/10.1109/iSES54909.2022.00033
RT T1 <cTitle>2022 IEEE International Symposium on Smart Electronic Systems (iSES)</cTitle>: T1 <Title>An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10026930&Exemplar=1&LAN=DE A1 Yanamala, Rama Muni Reddy A1 Pullakandam, Muralidhar YR 2022 K1 Visualization K1 Convolution K1 Image edge detection K1 Neurons K1 Memory management K1 System-on-chip K1 Convolutional neural networks K1 FPGA K1 Convolutional Neural Network K1 Hardware Accelerator K1 Python K1 PYNQ-Z2 K1 High Level Synthesis K1 Pipelining K1 Unrolling SP 112 OP 117 LK http://dx.doi.org/https://doi.org/10.1109/iSES54909.2022.00033 DO https://doi.org/10.1109/iSES54909.2022.00033 SF ELIB - SuUB Bremen
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