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1 Ergebnisse
1
HiPR: High-level Partial Reconfiguration for Fast Increment..:
, In:
2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
,
Xiao, Yuanlong
;
Hota, Aditya
;
Park, Dongjoon
. - p. 70-78 , 2022
Link:
https://doi.org/10.1109/FPL57034.2022.00022
RT T1
2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
: T1
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
UL https://suche.suub.uni-bremen.de/peid=ieee-10035173&Exemplar=1&LAN=DE A1 Xiao, Yuanlong A1 Hota, Aditya A1 Park, Dongjoon A1 DeHon, Andre YR 2022 SN 1946-1488 K1 Benchmark testing K1 Software K1 Hardware design languages K1 Field programmable gate arrays K1 FPGA K1 Incremental Compilation K1 Streams K1 Dataflow K1 Latency Insensitive K1 Partial Reconfiguration SP 70 OP 78 LK http://dx.doi.org/https://doi.org/10.1109/FPL57034.2022.00022 DO https://doi.org/10.1109/FPL57034.2022.00022 SF ELIB - SuUB Bremen
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