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1 Ergebnisse
1
Design and Implementation of Low Power Posit Arithmetic Uni..:
, In:
2022 10th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC)
,
Essam, Mohammed
;
Shalaby, Ahmed
;
Taher, Mohamed
- p. 68-71 , 2022
Link:
https://doi.org/10.1109/JAC-ECC56395.2022.10043893
RT T1 <cTitle>2022 10th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC)</cTitle>: T1 <Title>Design and Implementation of Low Power Posit Arithmetic Unit for Efficient Hardware Accelerators</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10043893&Exemplar=1&LAN=DE A1 Essam, Mohammed A1 Shalaby, Ahmed A1 Taher, Mohamed YR 2022 K1 Industries K1 Power demand K1 Logic gates K1 IEEE Standards K1 Resource management K1 Hardware design languages K1 Hardware acceleration K1 hardware accelerators K1 arithmetic logic unit K1 posit arithmetic K1 floating point arithmetic K1 adders K1 multipliers SP 68 OP 71 LK http://dx.doi.org/https://doi.org/10.1109/JAC-ECC56395.2022.10043893 DO https://doi.org/10.1109/JAC-ECC56395.2022.10043893 SF ELIB - SuUB Bremen
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