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A Design Method of High Parallelism QC-LDPC Decoder Based o..:
, In:
2022 5th International Conference on Information Communication and Signal Processing (ICICSP)
,
Bai, Haojie
;
Zhai, Keyuan
;
Liu, Guangzu
. - p. 441-447 , 2022
Link:
https://doi.org/10.1109/ICICSP55539.2022.10050584
RT T1 <cTitle>2022 5th International Conference on Information Communication and Signal Processing (ICICSP)</cTitle>: T1 <Title>A Design Method of High Parallelism QC-LDPC Decoder Based on FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10050584&Exemplar=1&LAN=DE A1 Bai, Haojie A1 Zhai, Keyuan A1 Liu, Guangzu A1 Zou, Jun YR 2022 SN 2770-792X K1 Design methodology K1 Signal processing algorithms K1 Parallel processing K1 Throughput K1 Parity check codes K1 Decoding K1 Error correction K1 QC-LDPC K1 Overlapped-NMSA K1 efficient storage addressing scheme K1 high-speed decoding SP 441 OP 447 LK http://dx.doi.org/https://doi.org/10.1109/ICICSP55539.2022.10050584 DO https://doi.org/10.1109/ICICSP55539.2022.10050584 SF ELIB - SuUB Bremen
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