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1
TCAD Analysis of Substrate Thickness of a 10nm Vertical Dou..:
, In:
2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT)
,
Varma, Srinivas
;
Chowdari, Ch Pratyusha
;
Panigrahi, Asisa Kumar
- p. 97-102 , 2023
Link:
https://doi.org/10.1109/ICSSIT55814.2023.10060965
RT T1 <cTitle>2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT)</cTitle>: T1 <Title>TCAD Analysis of Substrate Thickness of a 10nm Vertical Double Gate SOI n-Type MOSFET</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10060965&Exemplar=1&LAN=DE A1 Varma, Srinivas A1 Chowdari, Ch Pratyusha A1 Panigrahi, Asisa Kumar YR 2023 SN 2832-3017 K1 Semiconductor device modeling K1 Resistance K1 Silicon-on-insulator K1 Voltage K1 Logic gates K1 Software K1 Silicon K1 10nm Field Effect Transistor K1 Double Gate Transistor K1 Low Area K1 Analysis of Substrate Thickness SP 97 OP 102 LK http://dx.doi.org/https://doi.org/10.1109/ICSSIT55814.2023.10060965 DO https://doi.org/10.1109/ICSSIT55814.2023.10060965 SF ELIB - SuUB Bremen
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