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1 Ergebnisse
1
Delay Enhancement of Wallace Tree Multiplier with Binary to..:
, In:
2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT)
,
Ram, G. Challa
;
Subbarao, M. Venkata
;
Varma, D. Ramesh
. - p. 113-117 , 2023
Link:
https://doi.org/10.1109/ICSSIT55814.2023.10061043
RT T1 <cTitle>2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT)</cTitle>: T1 <Title>Delay Enhancement of Wallace Tree Multiplier with Binary to Excess-1 Converter</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10061043&Exemplar=1&LAN=DE A1 Ram, G. Challa A1 Subbarao, M. Venkata A1 Varma, D. Ramesh A1 Kumar, M. Prema YR 2023 SN 2832-3017 K1 Codes K1 Microprocessors K1 Memory management K1 Delays K1 Hardware design languages K1 Adders K1 Standards K1 Array multiplier K1 Binary to Excess-1 code (BEC) K1 Carry select adder (CSLA) K1 Kogge Stone Adder (KSA) K1 Ripple carry adder (RCA) K1 Wallace multiplier (WM) SP 113 OP 117 LK http://dx.doi.org/https://doi.org/10.1109/ICSSIT55814.2023.10061043 DO https://doi.org/10.1109/ICSSIT55814.2023.10061043 SF ELIB - SuUB Bremen
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