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VLSI Design of Pipelined FFT Architecture for DSP Applicati..:
, In:
2023 7th International Conference on Computing Methodologies and Communication (ICCMC)
,
Kumar T, Siva
;
K, Naveenraj
;
R, Ragupathi
. - p. 1617-1620 , 2023
Link:
https://doi.org/10.1109/ICCMC56507.2023.10083571
RT T1
2023 7th International Conference on Computing Methodologies and Communication (ICCMC)
: T1
VLSI Design of Pipelined FFT Architecture for DSP Application
UL https://suche.suub.uni-bremen.de/peid=ieee-10083571&Exemplar=1&LAN=DE A1 Kumar T, Siva A1 K, Naveenraj A1 R, Ragupathi A1 S, Ravip rasath YR 2023 K1 Power demand K1 Fast Fourier transforms K1 Power quality K1 Computer architecture K1 Very large scale integration K1 Hardware design languages K1 Field programmable gate arrays K1 The Shifter K1 Rotators K1 Pipelined register K1 Delay power analysis K1 Fast Fourier Transform and Inverse Fast Fourier Transform SP 1617 OP 1620 LK http://dx.doi.org/https://doi.org/10.1109/ICCMC56507.2023.10083571 DO https://doi.org/10.1109/ICCMC56507.2023.10083571 SF ELIB - SuUB Bremen
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