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A 16Gbps 3rd Order CTLE Design for Serial Links with High C..:
, In:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)
,
Thota, Pranay Kumar
;
Rapina, Siva Kumar
;
Nistala, Bheema Rao
- p. 284-289 , 2023
Link:
https://doi.org/10.1109/VLSID57277.2023.00065
RT T1 <cTitle>2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)</cTitle>: T1 <Title>A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10089943&Exemplar=1&LAN=DE A1 Thota, Pranay Kumar A1 Rapina, Siva Kumar A1 Nistala, Bheema Rao YR 2023 SN 2380-6923 K1 Equalizers K1 Symbols K1 Receivers K1 Interference K1 Very large scale integration K1 FinFETs K1 Transceivers K1 Equalizer K1 High speed link K1 Inter Symbol Interference (ISI) K1 Lossy channel K1 Broadband receivers SP 284 OP 289 LK http://dx.doi.org/https://doi.org/10.1109/VLSID57277.2023.00065 DO https://doi.org/10.1109/VLSID57277.2023.00065 SF ELIB - SuUB Bremen
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