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1 Ergebnisse
1
A Two-stage Training Framework for Hardware Constraints of ..:
, In:
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
,
Kuo, Hao-Wen
;
Wang, Rui-Hsuan
;
Li, Zhaofang
... - p. 30-34 , 2022
Link:
https://doi.org/10.1109/APCCAS55924.2022.10090308
RT T1 <cTitle>2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)</cTitle>: T1 <Title>A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10090308&Exemplar=1&LAN=DE A1 Kuo, Hao-Wen A1 Wang, Rui-Hsuan A1 Li, Zhaofang A1 Lin, Shih-Ting A1 Chang, Meng-Fan A1 Tang, Kea-Tiong YR 2022 K1 Training K1 Quantization (signal) K1 Convolution K1 Computational modeling K1 Neural networks K1 Computer architecture K1 Hardware K1 Quantization K1 Model Compression K1 Computing-in-Memory K1 Nonidealities K1 Deep Learning SP 30 OP 34 LK http://dx.doi.org/https://doi.org/10.1109/APCCAS55924.2022.10090308 DO https://doi.org/10.1109/APCCAS55924.2022.10090308 SF ELIB - SuUB Bremen
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