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1 Ergebnisse
1
Modified Efficient Parallel Distributed Arithmetic based FI..:
, In:
2023 10th International Conference on Signal Processing and Integrated Networks (SPIN)
,
Soni, Teena
;
Kumar, Anil
;
Panda, Manoj Kumar
- p. 860-865 , 2023
Link:
https://doi.org/10.1109/SPIN57001.2023.10116765
RT T1
2023 10th International Conference on Signal Processing and Integrated Networks (SPIN)
: T1
Modified Efficient Parallel Distributed Arithmetic based FIR Filter Architecture for ASIC and FPGA
UL https://suche.suub.uni-bremen.de/peid=ieee-10116765&Exemplar=1&LAN=DE A1 Soni, Teena A1 Kumar, Anil A1 Panda, Manoj Kumar YR 2023 SN 2688-769X K1 Measurement K1 Power demand K1 Finite impulse response filters K1 Signal processing algorithms K1 Computer architecture K1 Signal processing K1 Throughput K1 Distributed Arithmetic K1 FPGA K1 ASIC K1 FIR Filter K1 Multiplierless SP 860 OP 865 LK http://dx.doi.org/https://doi.org/10.1109/SPIN57001.2023.10116765 DO https://doi.org/10.1109/SPIN57001.2023.10116765 SF ELIB - SuUB Bremen
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