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1 Ergebnisse
1
Dual Vector Load for Improved Pipelining in Vector Processo..:
, In:
2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
,
Razilov, Viktor
;
Zhong, Juncen
;
Matus, Emil
. - p. 1-6 , 2023
Link:
https://doi.org/10.1109/COOLCHIPS57690.2023.10121996
RT T1
2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
: T1
Dual Vector Load for Improved Pipelining in Vector Processors
UL https://suche.suub.uni-bremen.de/peid=ieee-10121996&Exemplar=1&LAN=DE A1 Razilov, Viktor A1 Zhong, Juncen A1 Matus, Emil A1 Fettweis, Gerhard YR 2023 SN 2473-4683 K1 Bandwidth K1 Time division multiplexing K1 Hardware K1 Vector processors K1 Pipeline processing K1 RISC-V K1 dual load K1 vector processor K1 DSP SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/COOLCHIPS57690.2023.10121996 DO https://doi.org/10.1109/COOLCHIPS57690.2023.10121996 SF ELIB - SuUB Bremen
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