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1 Ergebnisse
1
Warpage Assessment of System in Wafer-level Package Technol..:
, In:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
,
Yu, Ching-Feng
;
Hsu, Chao-Kai
;
Hsiao, Chih-Cheng
- p. 1-2 , 2023
Link:
https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10..
RT T1 <cTitle>2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)</cTitle>: T1 <Title>Warpage Assessment of System in Wafer-level Package Technology with RDL Process through Theoretical Approach and Experimental Validation</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10134039&Exemplar=1&LAN=DE A1 Yu, Ching-Feng A1 Hsu, Chao-Kai A1 Hsiao, Chih-Cheng YR 2023 K1 Semiconductor device modeling K1 Fabrication K1 Solid modeling K1 Three-dimensional displays K1 Design methodology K1 Very large scale integration K1 Finite element analysis SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134039 DO https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134039 SF ELIB - SuUB Bremen
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