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1 Ergebnisse
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Demonstration of A 3D Chip by Logic-DRAM Stacked Using Pair..:
, In:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
,
Lu, Chun-Lin
;
Chen, Chun Cheng
;
Lin, Sheng-Chieh
... - p. 1-2 , 2023
Link:
https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10..
RT T1
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
: T1
Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application
UL https://suche.suub.uni-bremen.de/peid=ieee-10134092&Exemplar=1&LAN=DE A1 Lu, Chun-Lin A1 Chen, Chun Cheng A1 Lin, Sheng-Chieh A1 Chuang, Chih-Hao A1 Shih, Kai-Yao A1 Liao, Hsin-Yi A1 Huang, Chin-Hung A1 Ju, Min-Syong A1 Ho, Cheng-Shu A1 Chen, Chi Ming A1 Chang, Shou-Zen YR 2023 K1 Three-dimensional displays K1 Multiprocessor interconnection K1 Semiconductor device reliability K1 Metals K1 Very large scale integration K1 Contact resistance K1 Silicon SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134092 DO https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134092 SF ELIB - SuUB Bremen
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