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1 Ergebnisse
1
Improving the fabricated Rate and Reliability of Top Gate a..:
, In:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
,
Huang, Bo-Shen
;
Chang, Ting-Chang
;
Tai, Mao-Chou
. - p. 1-2 , 2023
Link:
https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10..
RT T1 <cTitle>2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)</cTitle>: T1 <Title>Improving the fabricated Rate and Reliability of Top Gate a-IGZO TFTs under Positive Bias Stress by Using Double-Stacked Gate Insulator Layer Design</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10134354&Exemplar=1&LAN=DE A1 Huang, Bo-Shen A1 Chang, Ting-Chang A1 Tai, Mao-Chou A1 Yen, Po-Yu YR 2023 K1 Degradation K1 Process design K1 Hydrogen K1 Logic gates K1 Very large scale integration K1 Reliability engineering K1 Insulators SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134354 DO https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134354 SF ELIB - SuUB Bremen
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