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1 Ergebnisse
1
FPGA Implementation of Area Efficient 16-Bit Vedic Multipli..:
, In:
2023 IEEE Devices for Integrated Circuit (DevIC)
,
Sairam, P
;
Manikumar, K
;
Reddy, Y Suresh
.. - p. 404-407 , 2023
Link:
https://doi.org/10.1109/DevIC57758.2023.10134837
RT T1
2023 IEEE Devices for Integrated Circuit (DevIC)
: T1
FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors
UL https://suche.suub.uni-bremen.de/peid=ieee-10134837&Exemplar=1&LAN=DE A1 Sairam, P A1 Manikumar, K A1 Reddy, Y Suresh A1 Narayana, B Uday A1 Gowreesrinivas, K.V. YR 2023 K1 Computer architecture K1 Logic gates K1 Compressors K1 Mathematics K1 Delays K1 Hardware design languages K1 Field programmable gate arrays K1 compressor K1 multiplier K1 xilinx K1 basys3 K1 vedic mathematics SP 404 OP 407 LK http://dx.doi.org/https://doi.org/10.1109/DevIC57758.2023.10134837 DO https://doi.org/10.1109/DevIC57758.2023.10134837 SF ELIB - SuUB Bremen
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