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1
Realization of Logic Performance using Double Gate TFET (DG..:
, In:
2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP)
,
Phulawariya, Hitesh Kumar
;
Chaudhary, Rashi
;
Tiwari, Shreyas
. - p. 1-5 , 2023
Link:
https://doi.org/10.1109/AISP57993.2023.10134840
RT T1
2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP)
: T1
Realization of Logic Performance using Double Gate TFET (DG-TFET) and Ge source DG-TFET (s-Ge-TFET)
UL https://suche.suub.uni-bremen.de/peid=ieee-10134840&Exemplar=1&LAN=DE A1 Phulawariya, Hitesh Kumar A1 Chaudhary, Rashi A1 Tiwari, Shreyas A1 Saha, Rajesh YR 2023 SN 2640-5768 K1 Visualization K1 TFETs K1 Photonic band gap K1 Logic gates K1 Signal processing K1 Germanium K1 Silicon K1 DG-TFET K1 Electrical Parameters K1 Inverter K1 NAND K1 NOR SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/AISP57993.2023.10134840 DO https://doi.org/10.1109/AISP57993.2023.10134840 SF ELIB - SuUB Bremen
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