I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Cross Layer Design for the Predictive Assessment of Technol..:
, In:
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
,
Niemier, M.
;
Hu, X.S.
;
Liu, L.
... - p. 1-10 , 2023
Link:
https://doi.org/10.23919/DATE56975.2023.10136923
RT T1 <cTitle>2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)</cTitle>: T1 <Title>Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10136923&Exemplar=1&LAN=DE A1 Niemier, M. A1 Hu, X.S. A1 Liu, L. A1 Sharifi, M. A1 O'Connor, Ian A1 Atienza, David A1 Ansaloni, Giovanni A1 Li, Can A1 Khan, Asif A1 Ralph, Daniel C. YR 2023 SN 1558-1101 K1 Analytical models K1 Technological innovation K1 Cross layer design K1 Systematics K1 Computational modeling K1 Collaboration K1 Computer architecture K1 Emerging logic and memory K1 cross-layer design K1 FeFETs K1 RRAM K1 design space explorations K1 device modeling K1 circuit modeling K1 architectural modeling K1 application analysis SP 1 OP 10 LK http://dx.doi.org/https://doi.org/10.23919/DATE56975.2023.10136923 DO https://doi.org/10.23919/DATE56975.2023.10136923 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
