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An Optimum Design and Implementation of a 16-bit ALU on CAD..:
, In:
2023 IEEE International Conference on Emerging Trends in Engineering, Sciences and Technology (ICES&T)
,
Raza, Muhammad Ali
;
Shahzad, Iraj
;
Anwar, Hafsa
... - p. 1-5 , 2023
Link:
https://doi.org/10.1109/ICEST56843.2023.10138869
RT T1 <cTitle>2023 IEEE International Conference on Emerging Trends in Engineering, Sciences and Technology (ICES&T)</cTitle>: T1 <Title>An Optimum Design and Implementation of a 16-bit ALU on CADENCE Using RISC-V Architecture</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10138869&Exemplar=1&LAN=DE A1 Raza, Muhammad Ali A1 Shahzad, Iraj A1 Anwar, Hafsa A1 Qureshi, Muhammad Ali A1 Malik, Farhan Hassan A1 Khan, Muhammad Usman Ali YR 2023 K1 Semiconductor device measurement K1 Power demand K1 Reduced instruction set computing K1 Computer architecture K1 Programming K1 Software K1 Central Processing Unit K1 Arithmetic Logic Unit (ALU) K1 Reduced Instruction Set Computer (RISC) K1 Complex Instruction Set Architecture (CISC) K1 Instruction Set Architecture (ISA) K1 CADENCE K1 Chip Design SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ICEST56843.2023.10138869 DO https://doi.org/10.1109/ICEST56843.2023.10138869 SF ELIB - SuUB Bremen
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