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1 Ergebnisse
1
An Exploration of ATPG Methods for Redacted IP and Reconfig..:
, In:
2023 IEEE 41st VLSI Test Symposium (VTS)
,
Fugate, Jackson
;
Stitt, Greg
;
Masna, Naren Vikram Raj
... - p. 1-7 , 2023
Link:
https://doi.org/10.1109/VTS56346.2023.10139957
RT T1
2023 IEEE 41st VLSI Test Symposium (VTS)
: T1
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware
UL https://suche.suub.uni-bremen.de/peid=ieee-10139957&Exemplar=1&LAN=DE A1 Fugate, Jackson A1 Stitt, Greg A1 Masna, Naren Vikram Raj A1 Dasgupta, Aritra A1 Bhunia, Swarup A1 Dorairaj, Nij A1 Kehlet, David YR 2023 SN 2375-1053 K1 Loading K1 Reverse engineering K1 Very large scale integration K1 Market research K1 Hardware K1 Encoding K1 IP networks K1 Hardware IP protection K1 Reverse Engineering K1 Piracy K1 Confidentiality K1 ATPG K1 IP redaction SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/VTS56346.2023.10139957 DO https://doi.org/10.1109/VTS56346.2023.10139957 SF ELIB - SuUB Bremen
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