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1 Ergebnisse
1
Design for testability (DFT) for RSFQ circuits:
, In:
2023 IEEE 41st VLSI Test Symposium (VTS)
,
Li, Mingye
;
Lin, Yunkun
;
Gupta, Sandeep
- p. 1-7 , 2023
Link:
https://doi.org/10.1109/VTS56346.2023.10139966
RT T1
2023 IEEE 41st VLSI Test Symposium (VTS)
: T1
Design for testability (DFT) for RSFQ circuits
UL https://suche.suub.uni-bremen.de/peid=ieee-10139966&Exemplar=1&LAN=DE A1 Li, Mingye A1 Lin, Yunkun A1 Gupta, Sandeep YR 2023 SN 2375-1053 K1 Temperature K1 Wires K1 Discrete Fourier transforms K1 Computer architecture K1 Very large scale integration K1 Delays K1 Temperature control K1 RSFQ K1 Design for testability (DFT) SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/VTS56346.2023.10139966 DO https://doi.org/10.1109/VTS56346.2023.10139966 SF ELIB - SuUB Bremen
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