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Substrate Noise Evaluation and Reduction of N-MOSFET Using ..:
, In:
2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC)
,
Sharma, Sanjay
;
Yadav, R. P.
;
Janyani, Vijay
- p. 1-6 , 2023
Link:
https://doi.org/10.1109/ESDC56251.2023.10149882
RT T1
2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC)
: T1
Substrate Noise Evaluation and Reduction of N-MOSFET Using Optimized Silicone-On-Insulator based on Seagull optimization algorithm
UL https://suche.suub.uni-bremen.de/peid=ieee-10149882&Exemplar=1&LAN=DE A1 Sharma, Sanjay A1 Yadav, R. P. A1 Janyani, Vijay YR 2023 K1 Semiconductor device modeling K1 MOSFET K1 Analytical models K1 Silicon-on-insulator K1 Voltage K1 MOSFET circuits K1 Logic gates K1 n-MOSFET K1 SOI K1 Al203 K1 Si3N4 K1 seagull optimization K1 substrate noise evaluation SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ESDC56251.2023.10149882 DO https://doi.org/10.1109/ESDC56251.2023.10149882 SF ELIB - SuUB Bremen
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