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1
Quick Computation of the Lower Bound on the Gate Count of T..:
, In:
2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL)
,
Hirayama, Takashi
;
Suzuki, Rin
;
Yamanaka, Katsuhisa
. - p. 153-157 , 2023
Link:
https://doi.org/10.1109/ISMVL57333.2023.00038
RT T1 <cTitle>2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL)</cTitle>: T1 <Title>Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10153893&Exemplar=1&LAN=DE A1 Hirayama, Takashi A1 Suzuki, Rin A1 Yamanaka, Katsuhisa A1 Nishitani, Yasuaki YR 2023 SN 2378-2226 K1 Logic circuits K1 Logic gates K1 Logic functions K1 Minimization K1 Proposals K1 Time complexity K1 reversible logic circuits K1 Toffoli gates K1 lower bound K1 logic minimization SP 153 OP 157 LK http://dx.doi.org/https://doi.org/10.1109/ISMVL57333.2023.00038 DO https://doi.org/10.1109/ISMVL57333.2023.00038 SF ELIB - SuUB Bremen
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