I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accele..:
, In:
2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
,
Zhou, Haoxiang
;
Hong, Haiqiao
;
Liu, Dingbang
... - p. 1-5 , 2023
Link:
https://doi.org/10.1109/AICAS57966.2023.10168630
RT T1
2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
: T1
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate
UL https://suche.suub.uni-bremen.de/peid=ieee-10168630&Exemplar=1&LAN=DE A1 Zhou, Haoxiang A1 Hong, Haiqiao A1 Liu, Dingbang A1 Liu, Hang A1 Xia, Yu A1 Li, Kai A1 Liu, Jun A1 Luo, Shaobo A1 Mao, Wei A1 Yu, Hao YR 2023 SN 2834-9857 K1 Power demand K1 Simulation K1 Random access memory K1 Throughput K1 Energy efficiency K1 Common Information Model (computing) K1 Hardware K1 CNN accelerator K1 SRAM K1 hardware utilization K1 data reuse K1 RISC-V SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/AICAS57966.2023.10168630 DO https://doi.org/10.1109/AICAS57966.2023.10168630 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)