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1
Synthesis of Reversible Logic Circuits-A Technical Review:
, In:
2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS)
,
Das, Bhaskar
;
Vinutha, N
;
Zafar, Nadiya
. - p. 309-313 , 2023
Link:
https://doi.org/10.1109/ICAECIS58353.2023.10170496
RT T1
2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS)
: T1
Synthesis of Reversible Logic Circuits-A Technical Review
UL https://suche.suub.uni-bremen.de/peid=ieee-10170496&Exemplar=1&LAN=DE A1 Das, Bhaskar A1 Vinutha, N A1 Zafar, Nadiya A1 Rajeshwar, Moghekar YR 2023 K1 Costs K1 Power demand K1 Logic circuits K1 Signal processing algorithms K1 Optical computing K1 Digital signal processing K1 Logic gates K1 BDD K1 ESOP K1 Logic Gate Synthesis K1 Reversible Logic SP 309 OP 313 LK http://dx.doi.org/https://doi.org/10.1109/ICAECIS58353.2023.10170496 DO https://doi.org/10.1109/ICAECIS58353.2023.10170496 SF ELIB - SuUB Bremen
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