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1
Architectures and Circuits for Analog-memory-based Hardware..:
, In:
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Tsai, Hsinyu
;
Narayanan, Pritish
;
Jain, Shubham
... - p. 1-5 , 2023
Link:
https://doi.org/10.1109/ISCAS46773.2023.10181650
RT T1
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
: T1
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)
UL https://suche.suub.uni-bremen.de/peid=ieee-10181650&Exemplar=1&LAN=DE A1 Tsai, Hsinyu A1 Narayanan, Pritish A1 Jain, Shubham A1 Ambrogio, Stefano A1 Hosokawa, Kohji A1 Ishii, Masatoshi A1 Mackin, Charles A1 Chen, Ching-Tzu A1 Okazaki, Atsuya A1 Nomura, Akiyo A1 Boybat, Irem A1 Muralidhar, Ramachandran A1 Frank, Martin M. A1 Yasuda, Takeo A1 Friz, Alexander A1 Kohda, Yasuteru A1 Chen, An A1 Fasoli, Andrea A1 Rasch, Malte J. A1 Wozniak, Stanislaw A1 Luquin, Jose A1 Narayanan, Vijay A1 Burr, Geoffrey W. YR 2023 SN 2158-1525 K1 Phased arrays K1 Phase change materials K1 Performance evaluation K1 Nonvolatile memory K1 Accelerator architectures K1 Artificial neural networks K1 Benchmark testing K1 In-memory computing K1 Non-volatile memory K1 inference K1 analog multiply-accumulate for DNNs K1 analog AI K1 deep learning accelerator K1 system modeling SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS46773.2023.10181650 DO https://doi.org/10.1109/ISCAS46773.2023.10181650 SF ELIB - SuUB Bremen
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