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1 Ergebnisse
1
Block-level Evaluation and Optimization of Backside PDN for..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Sisto, G.
;
Preston, R.
;
Chen, R.
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185211&Exemplar=1&LAN=DE A1 Sisto, G. A1 Preston, R. A1 Chen, R. A1 Mirabelli, G. A1 Farokhnejad, A. A1 Zhou, Y. A1 Ciofi, I. A1 Jourdain, A. A1 Veloso, A. A1 Stucchi, M. A1 Zografos, O. A1 Weckx, P. A1 Hellings, G. A1 Ryckaert, J. YR 2023 SN 2158-9682 K1 Resistance K1 Limiting K1 Switches K1 Very large scale integration K1 Tin K1 Business process re-engineering K1 Timing SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185211 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185211 SF ELIB - SuUB Bremen
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