I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduc..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Kim, Jeongkyun
;
Yook, Byungho
;
Choi, Taemin
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185223&Exemplar=1&LAN=DE A1 Kim, Jeongkyun A1 Yook, Byungho A1 Choi, Taemin A1 Choi, Kyuwon A1 Lee, Chanho A1 Li, Yunrong A1 Lee, Youngo A1 Yun, Seok A1 Do, Changhoon A1 Tang, Hoyoung A1 Lee, Inhak A1 Seo, Dongwook A1 Baeck, Sangyeop YR 2023 SN 2158-9682 K1 High performance computing K1 Loading K1 Random access memory K1 Computer architecture K1 Very large scale integration K1 Logic gates K1 FinFETs K1 Pseudo Two-port SRAM K1 High Speed K1 BL Pre-Charge Control K1 Flying Word-line SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185223 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185223 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
