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1 Ergebnisse
1
Ultra-high Tunneling Electroresistance Ratio (2 × 104) & En..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Hwang, Junghyeon
;
Kim, Chaeheon
;
Shin, Hunbeom
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185231&Exemplar=1&LAN=DE A1 Hwang, Junghyeon A1 Kim, Chaeheon A1 Shin, Hunbeom A1 Kim, Hwayoung A1 Park, Sang-Hee Ko A1 Jeon, Sanghun YR 2023 SN 2158-9682 K1 Neural networks K1 Discrete Fourier transforms K1 Very large scale integration K1 Tunneling K1 Junctions K1 Synapses SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185231 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185231 SF ELIB - SuUB Bremen
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