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1 Ergebnisse
1
A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) us..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Choe, Jeongwon
;
Lee, Youngjoo
- p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
: T1
A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-10185244&Exemplar=1&LAN=DE A1 Choe, Jeongwon A1 Lee, Youngjoo YR 2023 SN 2158-9682 K1 Costs K1 Codes K1 Memory management K1 Prototypes K1 Very large scale integration K1 CMOS process K1 Decoding K1 Error-correction code K1 NB-LDPC decoder K1 VLSI SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185244 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185244 SF ELIB - SuUB Bremen
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