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1 Ergebnisse
1
Characterizing and Reducing the Layout Dependent Effect and..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Lu, C.A.
;
Lee, H.P.
;
Chen, H.C.
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185282&Exemplar=1&LAN=DE A1 Lu, C.A. A1 Lee, H.P. A1 Chen, H.C. A1 Lin, Y.C. A1 Chung, Y.H. A1 Wang, S.H. A1 Yeh, J.Y. A1 Chang, V.S. A1 Chiang, M.C. A1 Chang, W. A1 Chung, H.C. A1 Cheng, C.F. A1 Hsu, H.H. A1 Liu, H.H. A1 Chen, William P.N. A1 Lin, C.Y. YR 2023 SN 2158-9682 K1 Resistance K1 Performance evaluation K1 Layout K1 Metals K1 Voltage K1 Logic gates K1 Very large scale integration SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185282 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185282 SF ELIB - SuUB Bremen
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