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1 Ergebnisse
1
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Osada, Yoshiaki
;
Nakazato, Takaaki
;
Nii, Koji
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185289&Exemplar=1&LAN=DE A1 Osada, Yoshiaki A1 Nakazato, Takaaki A1 Nii, Koji A1 Liaw, Jhon-Jhy A1 Wu, Shien-Yang Michael A1 Li, Quincy A1 Fujiwara, Hidehiro A1 Liao, Hung-Jen A1 Chang, Tsung-Yung Jonathan YR 2023 SN 2158-9682 K1 Random access memory K1 Voltage K1 Very large scale integration K1 FinFETs K1 Driver circuits K1 SRAM K1 3nm FinFET K1 Cache family K1 Wordline driver sleep K1 Write driver sleep SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185289 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185289 SF ELIB - SuUB Bremen
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