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BEOL Interconnect Innovation: Materials, Process and System..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),

Thareja, Gaurav ; Pal, Ashish ; Wang, Xingye... - p. 1-2 , 2023

Link: https://doi.org/10.23919/VLSITechnologyandCir57934.202..

RT 
T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-10185299&Exemplar=1&LAN=DE
				
A1 Thareja, Gaurav
A1 Pal, Ashish
A1 Wang, Xingye
A1 Dag, Sefa
A1 You, Shi
A1 Sharma, Shashank
A1 Zhu, Qing
A1 Cervantes, Carmen L.
A1 Hwang, Shinjae
A1 Spuller, Matthew
A1 Ng, Ben
A1 Kumar, Pradeep S.
A1 Tam, Norman
A1 Gage, Max
A1 Deshpande, Sameer
A1 Wu, Zhiyuan
A1 Jansen, Alexander
A1 Dey, Liton
A1 Chen, Feng
A1 Xie, Xianjin
A1 Kashefizadeh, Keyvan
A1 Reddy, Vinod
A1 Lo, Andy
A1 Chen, Zhebo
A1 Huey, Sidney
A1 Tang, Jianshe
A1 Ren, He
A1 Naik, Mehul
A1 Brown, Brian
A1 Kesapragada, Sree
A1 Sangamali, Buvna Ayyagari-
A1 Bazizi, El Mehdi
A1 Tang, Xianmin
YR 2023
SN 2158-9682
K1 Resistance
K1 Grain boundaries
K1 Technological innovation
K1 Annealing
K1 Hydrogen
K1 Performance gain
K1 Very large scale integration
SP 1
OP 2
LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185299
DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185299
SF ELIB - SuUB Bremen

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