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1 Ergebnisse
1
16-layer 3D Vertical RRAM with Low Read Latency (18ns), Hig..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Ding, Yaxin
;
Yang, Jianguo
;
Liu, Yu
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185341&Exemplar=1&LAN=DE A1 Ding, Yaxin A1 Yang, Jianguo A1 Liu, Yu A1 Gao, Jianfeng A1 Wang, Yuan A1 Jiang, Pengfei A1 Lv, Shuxian A1 Chen, Yuting A1 Wang, Boping A1 Wei, Wei A1 Gong, Tiancheng A1 Xue, Kan-Hao A1 Luo, Qing A1 Miao, Xiangshui A1 Liu, Ming YR 2023 SN 2158-9682 K1 Performance evaluation K1 Three-dimensional displays K1 Very large scale integration K1 Sensors K1 Leakage currents K1 Current density SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185341 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185341 SF ELIB - SuUB Bremen
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