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1 Ergebnisse
1
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Tao, Weichen
;
Zhao, Weichen
;
Staszewski, Robert Bogdan
.. - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185415&Exemplar=1&LAN=DE A1 Tao, Weichen A1 Zhao, Weichen A1 Staszewski, Robert Bogdan A1 Lin, Fujiang A1 Hu, Yizhe YR 2023 SN 2158-9682 K1 Capacitors K1 Prototypes K1 Very large scale integration K1 Jitter K1 CMOS technology K1 Phase locked loops K1 Digital filters K1 Charge-steering-sampling (CSS) K1 ADPLL K1 subsampling K1 phase detection K1 low-jitter K1 5G K1 mm-wave SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185415 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185415 SF ELIB - SuUB Bremen
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