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1 Ergebnisse
1
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Tra..:
, In:
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Younis, Mohamed Badr
;
Ahmed, Mostafa
;
Wang, Tianyu
... - p. 1-2 , 2023
Link:
https://doi.org/10.23919/VLSITechnologyandCir57934.202..
RT T1 <cTitle>2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10185437&Exemplar=1&LAN=DE A1 Younis, Mohamed Badr A1 Ahmed, Mostafa A1 Wang, Tianyu A1 Abdelrahman, Ahmed A1 Khalil, Mahmoud A1 Jose, Anup A1 Hanumolu, Pavan Kumar YR 2023 SN 2158-9682 K1 Tracking loops K1 Power supplies K1 Air gaps K1 Very large scale integration K1 CMOS process K1 Transceivers K1 Energy efficiency SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185437 DO https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185437 SF ELIB - SuUB Bremen
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