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1
Designing Secure Performance Metrics for Last Level Cache:
, In:
2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
,
Roy, Probir
;
Eshete, Birhanu
;
Su, Pengfei
- p. 383-392 , 2023
Link:
https://doi.org/10.1109/IPDPSW59300.2023.00069
RT T1 <cTitle>2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)</cTitle>: T1 <Title>Designing Secure Performance Metrics for Last Level Cache</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10196544&Exemplar=1&LAN=DE A1 Roy, Probir A1 Eshete, Birhanu A1 Su, Pengfei YR 2023 K1 Measurement K1 Resistance K1 Privacy K1 Systematics K1 Side-channel attacks K1 Quality of service K1 Hardware K1 Performance monitoring K1 security K1 side channel attack K1 cache SP 383 OP 392 LK http://dx.doi.org/https://doi.org/10.1109/IPDPSW59300.2023.00069 DO https://doi.org/10.1109/IPDPSW59300.2023.00069 SF ELIB - SuUB Bremen
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