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1 Ergebnisse
1
HDLcs1.0: A Compiler and Simulator Framework for Hardware D..:
, In:
2023 International Symposium of Electronics Design Automation (ISEDA)
,
Meng, Liu
;
Shuai, Li
;
Yunfei, Wang
... - p. 93-96 , 2023
Link:
https://doi.org/10.1109/ISEDA59274.2023.10218422
RT T1 <cTitle>2023 International Symposium of Electronics Design Automation (ISEDA)</cTitle>: T1 <Title>HDLcs1.0: A Compiler and Simulator Framework for Hardware Description Language</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10218422&Exemplar=1&LAN=DE A1 Meng, Liu A1 Shuai, Li A1 Yunfei, Wang A1 Huixin, Peng A1 Chunxue, Liu A1 Liang, Wang YR 2023 K1 Integrated circuits K1 Design automation K1 Logic gates K1 Hardware design languages K1 Standards K1 Optimization K1 Open source software K1 Verilog HDL K1 compiler K1 simulator K1 RTL SP 93 OP 96 LK http://dx.doi.org/https://doi.org/10.1109/ISEDA59274.2023.10218422 DO https://doi.org/10.1109/ISEDA59274.2023.10218422 SF ELIB - SuUB Bremen
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