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1 Ergebnisse
1
Topology Generic DC-Model for Accelerating Analog Circuit O..:
, In:
2023 International Symposium of Electronics Design Automation (ISEDA)
,
Wang, Yuan
;
Xin, Jian
;
Fang, Jiahao
... - p. 65-70 , 2023
Link:
https://doi.org/10.1109/ISEDA59274.2023.10218550
RT T1 <cTitle>2023 International Symposium of Electronics Design Automation (ISEDA)</cTitle>: T1 <Title>Topology Generic DC-Model for Accelerating Analog Circuit Optimization</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10218550&Exemplar=1&LAN=DE A1 Wang, Yuan A1 Xin, Jian A1 Fang, Jiahao A1 Chen, Xiaofeng A1 Liu, Haixu A1 Qin, Qian A1 Chai, Chenkai A1 Lu, Yukai A1 Hao, Jinglei A1 Xiao, Jianhao A1 Ye, Zuochang A1 Wang, Yan YR 2023 K1 Network topology K1 Predictive models K1 Analog circuits K1 Prediction algorithms K1 Libraries K1 Graph neural networks K1 Topology K1 analog reuse K1 OTA K1 DC parameters K1 graph neural network K1 graph representation SP 65 OP 70 LK http://dx.doi.org/https://doi.org/10.1109/ISEDA59274.2023.10218550 DO https://doi.org/10.1109/ISEDA59274.2023.10218550 SF ELIB - SuUB Bremen
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