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1 Ergebnisse
1
Impact of layout and channel processing on CMOS low frequen..:
, In:
ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)
,
Simioni, Fausto
;
Labate, Lorenzo
;
Savio, Daniele
... - p. 17-20 , 2023
Link:
https://doi.org/10.1109/ESSDERC59256.2023.10268528
RT T1
ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)
: T1
Impact of layout and channel processing on CMOS low frequency noise variability
UL https://suche.suub.uni-bremen.de/peid=ieee-10268528&Exemplar=1&LAN=DE A1 Simioni, Fausto A1 Labate, Lorenzo A1 Savio, Daniele A1 Brizzi, Mariella A1 Ottogalli, Federica A1 Marchetti, Riccardo A1 Brazzelli, Silvia A1 Rossetti, Mattia YR 2023 SN 2378-6558 K1 Performance evaluation K1 Resistance K1 Low voltage K1 Impedance matching K1 Layout K1 Implants K1 Logic gates K1 Variability K1 Flicker Noise K1 RTN K1 layout SP 17 OP 20 LK http://dx.doi.org/https://doi.org/10.1109/ESSDERC59256.2023.10268528 DO https://doi.org/10.1109/ESSDERC59256.2023.10268528 SF ELIB - SuUB Bremen
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