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A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplie..:

, In: ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC),

Gupta, Mohit ; Cosemans, Stefan ; Debacker, Peter. - p. 417-420 , 2023

Link: https://doi.org/10.1109/ESSCIRC59616.2023.10268763

RT 
T1 <cTitle>ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)</cTitle>: T1 <Title>A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-10268763&Exemplar=1&LAN=DE
				
A1 Gupta, Mohit
A1 Cosemans, Stefan
A1 Debacker, Peter
A1 Dehaene, Wim
YR 2023
SN 2643-1319
K1 Semiconductor device measurement
K1 Low voltage
K1 Image edge detection
K1 Artificial neural networks
K1 Parallel processing
K1 In-memory computing
K1 Throughput
K1 6T-SRAM
K1 bit-serial arithmetic
K1 flexible bit-width
K1 in-memory computing (IMC)
K1 near-memory computing
K1 memory
K1 SRAM
K1 binary weights
K1 convolutional neural networks (CNNs)
K1 Fully connected (FC)
K1 dot-product
K1 edge-computing
K1 energy-efficient SRAM
SP 417
OP 420
LK http://dx.doi.org/https://doi.org/10.1109/ESSCIRC59616.2023.10268763
DO https://doi.org/10.1109/ESSCIRC59616.2023.10268763
SF ELIB - SuUB Bremen

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