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1 Ergebnisse
1
Low Power Performance Analysis of 16-Bit Vedic Math RISC Pr..:
, In:
2023 3rd Asian Conference on Innovation in Technology (ASIANCON)
,
Ahemd Khan, Pattan Shahnawaz
;
Vandana, B
;
Sai Deepak, Muddamshetty V V
. - p. 1-6 , 2023
Link:
https://doi.org/10.1109/ASIANCON58793.2023.10270703
RT T1
2023 3rd Asian Conference on Innovation in Technology (ASIANCON)
: T1
Low Power Performance Analysis of 16-Bit Vedic Math RISC Processor
UL https://suche.suub.uni-bremen.de/peid=ieee-10270703&Exemplar=1&LAN=DE A1 Ahemd Khan, Pattan Shahnawaz A1 Vandana, B A1 Sai Deepak, Muddamshetty V V A1 Baddam, Keerthana Reddy YR 2023 K1 Technological innovation K1 Reduced instruction set computing K1 Power demand K1 Systematics K1 Computer architecture K1 Delays K1 Table lookup K1 RISC Processor K1 Low-Power K1 ALU K1 MAC K1 RCA K1 Vedic Mathematics K1 Urdhva-Triyagbhyam Vedic Sutra SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ASIANCON58793.2023.10270703 DO https://doi.org/10.1109/ASIANCON58793.2023.10270703 SF ELIB - SuUB Bremen
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