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1 Ergebnisse
1
Accelerating SpMV on FPGAs Through Block-Row Compress: A Ta..:
, In:
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
,
Oliver, Jose
;
Alvarez, Carlos
;
Cervero, Teresa
... - p. 151-158 , 2023
Link:
https://doi.org/10.1109/FPL60245.2023.00029
RT T1
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
: T1
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach
UL https://suche.suub.uni-bremen.de/peid=ieee-10296357&Exemplar=1&LAN=DE A1 Oliver, Jose A1 Alvarez, Carlos A1 Cervero, Teresa A1 Martorell, Xavier A1 Davis, John D. A1 Ayguade, Eduard YR 2023 SN 1946-1488 K1 Scalability K1 Memory management K1 Encoding K1 System-on-chip K1 Sparse matrices K1 Proposals K1 Task analysis K1 FPGA K1 SpMV K1 HBM K1 HLS K1 FP64 K1 double-precision K1 High-performance computing K1 Sparse matrix representation SP 151 OP 158 LK http://dx.doi.org/https://doi.org/10.1109/FPL60245.2023.00029 DO https://doi.org/10.1109/FPL60245.2023.00029 SF ELIB - SuUB Bremen
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