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1
Front-End Design of 64-Bit Carry Look Ahead Adder:
, In:
2023 International Conference on Sustainable Emerging Innovations in Engineering and Technology (ICSEIET)
,
Bansal, Harsh Kumar
;
Singh, Teena
;
Karna, Rajnish Ranjan
.. - p. 281-285 , 2023
Link:
https://doi.org/10.1109/ICSEIET58677.2023.10303492
RT T1 <cTitle>2023 International Conference on Sustainable Emerging Innovations in Engineering and Technology (ICSEIET)</cTitle>: T1 <Title>Front-End Design of 64-Bit Carry Look Ahead Adder</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10303492&Exemplar=1&LAN=DE A1 Bansal, Harsh Kumar A1 Singh, Teena A1 Karna, Rajnish Ranjan A1 Gupta, Nitish A1 Sharma, Tripti YR 2023 K1 Technological innovation K1 Power demand K1 Digital signal processing K1 Computer architecture K1 Very large scale integration K1 Streaming media K1 Delays K1 Adder K1 Carry-Look-ahead adder K1 Verilog K1 computational time K1 (OCLA) Optimized Carry Look Ahead Adder SP 281 OP 285 LK http://dx.doi.org/https://doi.org/10.1109/ICSEIET58677.2023.10303492 DO https://doi.org/10.1109/ICSEIET58677.2023.10303492 SF ELIB - SuUB Bremen
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