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1 Ergebnisse
1
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MT..:
, In:
2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
,
Wijeratne, Sasindu
;
Kannan, Rajgopal
;
Prasanna, Viktor
- p. 23-33 , 2023
Link:
https://doi.org/10.1109/SBAC-PAD59825.2023.00012
RT T1
2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
: T1
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU
UL https://suche.suub.uni-bremen.de/peid=ieee-10305957&Exemplar=1&LAN=DE A1 Wijeratne, Sasindu A1 Kannan, Rajgopal A1 Prasanna, Viktor YR 2023 SN 2643-3001 K1 Tensors K1 Instruction sets K1 High performance computing K1 Heuristic algorithms K1 Layout K1 Computer architecture K1 Load management K1 Tensor Decomposition K1 spMTTKRP K1 CPU SP 23 OP 33 LK http://dx.doi.org/https://doi.org/10.1109/SBAC-PAD59825.2023.00012 DO https://doi.org/10.1109/SBAC-PAD59825.2023.00012 SF ELIB - SuUB Bremen
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