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1 Ergebnisse
1
Implementation of Low Power and High Speed Dadda Multiplier..:
, In:
2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)
,
Kumar, B. Ravi
;
Munaswamy, P.
;
Naik, B. Chandrababu
. - p. 1-7 , 2023
Link:
https://doi.org/10.1109/ICCCNT56998.2023.10307240
RT T1
2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)
: T1
Implementation of Low Power and High Speed Dadda Multiplier using Xor-Xnor cell Based Hybrid Logic Full Adder
UL https://suche.suub.uni-bremen.de/peid=ieee-10307240&Exemplar=1&LAN=DE A1 Kumar, B. Ravi A1 Munaswamy, P. A1 Naik, B. Chandrababu A1 Swetha, K. YR 2023 SN 2473-7674 K1 Architecture K1 Signal processing algorithms K1 Voltage K1 Digital signal processing K1 Computer architecture K1 FinFETs K1 Hybrid power systems K1 Xor-Xnor cell K1 18nm FinFET K1 Hybrid logic full adder K1 dadda multiplier SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/ICCCNT56998.2023.10307240 DO https://doi.org/10.1109/ICCCNT56998.2023.10307240 SF ELIB - SuUB Bremen
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